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<div class="title">xaxivdma_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gaebbb18b57a2957ab4a90b54c4f557fea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaebbb18b57a2957ab4a90b54c4f557fea">XAXIVDMA_MISMATCH_ERROR</a>&#160;&#160;&#160;0x80000010</td></tr>
<tr class="memdesc:gaebbb18b57a2957ab4a90b54c4f557fea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frame/Line Mismatch Error This is a typical DMA Internal Error, which on detection doesnt require a reset (as opposed to other errors).  <a href="group__axivdma__v6__0.html#gaebbb18b57a2957ab4a90b54c4f557fea">More...</a><br /></td></tr>
<tr class="separator:gaebbb18b57a2957ab4a90b54c4f557fea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac657067221649df8f259f9215bfba75e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gac657067221649df8f259f9215bfba75e">XAxiVdma_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XAxiVdma_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:gac657067221649df8f259f9215bfba75e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the given register.  <a href="group__axivdma__v6__0.html#gac657067221649df8f259f9215bfba75e">More...</a><br /></td></tr>
<tr class="separator:gac657067221649df8f259f9215bfba75e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga28900a15d22fc5a3729dfa102f5cbec9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga28900a15d22fc5a3729dfa102f5cbec9">XAxiVdma_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;XAxiVdma_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="memdesc:ga28900a15d22fc5a3729dfa102f5cbec9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write the given register.  <a href="group__axivdma__v6__0.html#ga28900a15d22fc5a3729dfa102f5cbec9">More...</a><br /></td></tr>
<tr class="separator:ga28900a15d22fc5a3729dfa102f5cbec9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Buffer Descriptor Alignment</div></td></tr>
<tr class="memitem:ga6f1b98d0a6280da333bc1a97adea974e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga6f1b98d0a6280da333bc1a97adea974e">XAXIVDMA_BD_MINIMUM_ALIGNMENT</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:ga6f1b98d0a6280da333bc1a97adea974e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Minimum byte alignment requirement for descriptors.  <a href="group__axivdma__v6__0.html#ga6f1b98d0a6280da333bc1a97adea974e">More...</a><br /></td></tr>
<tr class="separator:ga6f1b98d0a6280da333bc1a97adea974e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad0a3a99c4177ed92eda1616fca2fcfb1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gad0a3a99c4177ed92eda1616fca2fcfb1">XAXIVDMA_BD_MINIMUM_ALIGNMENT_WD</a>&#160;&#160;&#160;0x8</td></tr>
<tr class="memdesc:gad0a3a99c4177ed92eda1616fca2fcfb1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Minimum word alignment requirement for descriptors.  <a href="group__axivdma__v6__0.html#gad0a3a99c4177ed92eda1616fca2fcfb1">More...</a><br /></td></tr>
<tr class="separator:gad0a3a99c4177ed92eda1616fca2fcfb1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga74cbf8945ca6cf9175bac9d7ad21a1bf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga74cbf8945ca6cf9175bac9d7ad21a1bf">XAXIVDMA_MAX_FRAMESTORE</a>&#160;&#160;&#160;32</td></tr>
<tr class="memdesc:ga74cbf8945ca6cf9175bac9d7ad21a1bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of the frame store.  <a href="group__axivdma__v6__0.html#ga74cbf8945ca6cf9175bac9d7ad21a1bf">More...</a><br /></td></tr>
<tr class="separator:ga74cbf8945ca6cf9175bac9d7ad21a1bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed6082e7154b873435b6e0cbd6f7bf03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaed6082e7154b873435b6e0cbd6f7bf03">XAXIVDMA_MAX_FRAMESTORE_64</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gaed6082e7154b873435b6e0cbd6f7bf03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum # of the frame store for 64 bit.  <a href="group__axivdma__v6__0.html#gaed6082e7154b873435b6e0cbd6f7bf03">More...</a><br /></td></tr>
<tr class="separator:gaed6082e7154b873435b6e0cbd6f7bf03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Maximum transfer length</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This is determined by hardware </p>
</div></td></tr>
<tr class="memitem:ga675991fc9f37eb104afcd1b6e785a5c3"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_MAX_VSIZE</b>&#160;&#160;&#160;0x1FFF  /* Max vertical size, 8K */</td></tr>
<tr class="separator:ga675991fc9f37eb104afcd1b6e785a5c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ca61fa345c760ec0532c209c8cc06bd"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_MAX_HSIZE</b>&#160;&#160;&#160;0xFFFF  /* Max horizontal size, 64K */</td></tr>
<tr class="separator:ga7ca61fa345c760ec0532c209c8cc06bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga243cc3f529218b3edbc954d43cf02c3e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_MAX_STRIDE</b>&#160;&#160;&#160;0xFFFF  /* Max stride size, 64K */</td></tr>
<tr class="separator:ga243cc3f529218b3edbc954d43cf02c3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaecab8ebcc9f83abc6b88289fb11b9440"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaecab8ebcc9f83abc6b88289fb11b9440">XAXIVDMA_FRMDLY_MAX</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:gaecab8ebcc9f83abc6b88289fb11b9440"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum frame delay.  <a href="group__axivdma__v6__0.html#gaecab8ebcc9f83abc6b88289fb11b9440">More...</a><br /></td></tr>
<tr class="separator:gaecab8ebcc9f83abc6b88289fb11b9440"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register sets on TX (Read) and RX (Write) channels are identical</p>
<p>The version register is shared by both channels </p>
</div></td></tr>
<tr class="memitem:gae1497f30a25302cb0f4ec93a16a23100"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gae1497f30a25302cb0f4ec93a16a23100">XAXIVDMA_TX_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:gae1497f30a25302cb0f4ec93a16a23100"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX channel registers base.  <a href="group__axivdma__v6__0.html#gae1497f30a25302cb0f4ec93a16a23100">More...</a><br /></td></tr>
<tr class="separator:gae1497f30a25302cb0f4ec93a16a23100"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab97c05cd73a22a627177554199efb526"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gab97c05cd73a22a627177554199efb526">XAXIVDMA_RX_OFFSET</a>&#160;&#160;&#160;0x00000030</td></tr>
<tr class="memdesc:gab97c05cd73a22a627177554199efb526"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX channel registers base.  <a href="group__axivdma__v6__0.html#gab97c05cd73a22a627177554199efb526">More...</a><br /></td></tr>
<tr class="separator:gab97c05cd73a22a627177554199efb526"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga311f4eadce692b10effb8cd492b2120c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga311f4eadce692b10effb8cd492b2120c">XAXIVDMA_PARKPTR_OFFSET</a>&#160;&#160;&#160;0x00000028</td></tr>
<tr class="memdesc:ga311f4eadce692b10effb8cd492b2120c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Park Pointer Register.  <a href="group__axivdma__v6__0.html#ga311f4eadce692b10effb8cd492b2120c">More...</a><br /></td></tr>
<tr class="separator:ga311f4eadce692b10effb8cd492b2120c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga727fc3fe53b19cda302295ad25fe71a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga727fc3fe53b19cda302295ad25fe71a2">XAXIVDMA_VERSION_OFFSET</a>&#160;&#160;&#160;0x0000002C</td></tr>
<tr class="memdesc:ga727fc3fe53b19cda302295ad25fe71a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version register.  <a href="group__axivdma__v6__0.html#ga727fc3fe53b19cda302295ad25fe71a2">More...</a><br /></td></tr>
<tr class="separator:ga727fc3fe53b19cda302295ad25fe71a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb4ad98d2088b8488c6ec4e519449e36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gadb4ad98d2088b8488c6ec4e519449e36">XAXIVDMA_CR_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:gadb4ad98d2088b8488c6ec4e519449e36"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel control.  <a href="group__axivdma__v6__0.html#gadb4ad98d2088b8488c6ec4e519449e36">More...</a><br /></td></tr>
<tr class="separator:gadb4ad98d2088b8488c6ec4e519449e36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0617c0c161fd2d93690e2d3b0a0906b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga0617c0c161fd2d93690e2d3b0a0906b8">XAXIVDMA_SR_OFFSET</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga0617c0c161fd2d93690e2d3b0a0906b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status.  <a href="group__axivdma__v6__0.html#ga0617c0c161fd2d93690e2d3b0a0906b8">More...</a><br /></td></tr>
<tr class="separator:ga0617c0c161fd2d93690e2d3b0a0906b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga36d711874a8831f2b134a377488aefd2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga36d711874a8831f2b134a377488aefd2">XAXIVDMA_CDESC_OFFSET</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga36d711874a8831f2b134a377488aefd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current descriptor pointer.  <a href="group__axivdma__v6__0.html#ga36d711874a8831f2b134a377488aefd2">More...</a><br /></td></tr>
<tr class="separator:ga36d711874a8831f2b134a377488aefd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a1e429317226b3d7a3e9ee29688c3ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga8a1e429317226b3d7a3e9ee29688c3ab">XAXIVDMA_TDESC_OFFSET</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga8a1e429317226b3d7a3e9ee29688c3ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tail descriptor pointer.  <a href="group__axivdma__v6__0.html#ga8a1e429317226b3d7a3e9ee29688c3ab">More...</a><br /></td></tr>
<tr class="separator:ga8a1e429317226b3d7a3e9ee29688c3ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8d67525132073b0a56a57233c9038c8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga8d67525132073b0a56a57233c9038c8a">XAXIVDMA_HI_FRMBUF_OFFSET</a>&#160;&#160;&#160;0x00000014</td></tr>
<tr class="memdesc:ga8d67525132073b0a56a57233c9038c8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">32 FrameBuf Sel  <a href="group__axivdma__v6__0.html#ga8d67525132073b0a56a57233c9038c8a">More...</a><br /></td></tr>
<tr class="separator:ga8d67525132073b0a56a57233c9038c8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc02fa25db65faceed9fd49ee88fb609"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gacc02fa25db65faceed9fd49ee88fb609">XAXIVDMA_FRMSTORE_OFFSET</a>&#160;&#160;&#160;0x00000018</td></tr>
<tr class="memdesc:gacc02fa25db65faceed9fd49ee88fb609"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frame Store.  <a href="group__axivdma__v6__0.html#gacc02fa25db65faceed9fd49ee88fb609">More...</a><br /></td></tr>
<tr class="separator:gacc02fa25db65faceed9fd49ee88fb609"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad1bc694180b959ab0794ac6c4468a8ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gad1bc694180b959ab0794ac6c4468a8ba">XAXIVDMA_BUFTHRES_OFFSET</a>&#160;&#160;&#160;0x0000001C</td></tr>
<tr class="memdesc:gad1bc694180b959ab0794ac6c4468a8ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Buffer Thres.  <a href="group__axivdma__v6__0.html#gad1bc694180b959ab0794ac6c4468a8ba">More...</a><br /></td></tr>
<tr class="separator:gad1bc694180b959ab0794ac6c4468a8ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d94757e1f4835c0975b13f0ab543f8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga6d94757e1f4835c0975b13f0ab543f8b">XAXIVDMA_MM2S_ADDR_OFFSET</a>&#160;&#160;&#160;0x00000050</td></tr>
<tr class="memdesc:ga6d94757e1f4835c0975b13f0ab543f8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">MM2S channel Addr.  <a href="group__axivdma__v6__0.html#ga6d94757e1f4835c0975b13f0ab543f8b">More...</a><br /></td></tr>
<tr class="separator:ga6d94757e1f4835c0975b13f0ab543f8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8daae8241a3aeae54627939188febf71"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga8daae8241a3aeae54627939188febf71">XAXIVDMA_S2MM_ADDR_OFFSET</a>&#160;&#160;&#160;0x000000A0</td></tr>
<tr class="memdesc:ga8daae8241a3aeae54627939188febf71"><td class="mdescLeft">&#160;</td><td class="mdescRight">S2MM channel Addr.  <a href="group__axivdma__v6__0.html#ga8daae8241a3aeae54627939188febf71">More...</a><br /></td></tr>
<tr class="separator:ga8daae8241a3aeae54627939188febf71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae3281565e12c47c4888e228ec6a59e3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gae3281565e12c47c4888e228ec6a59e3c">XAXIVDMA_S2MM_DMA_IRQ_MASK_OFFSET</a>&#160;&#160;&#160;0x0000003C</td></tr>
<tr class="memdesc:gae3281565e12c47c4888e228ec6a59e3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">S2MM Err IRQ Mask.  <a href="group__axivdma__v6__0.html#gae3281565e12c47c4888e228ec6a59e3c">More...</a><br /></td></tr>
<tr class="separator:gae3281565e12c47c4888e228ec6a59e3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Start Addresses Register Array for a Channel</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Base offset is set in each channel This set of registers are write only, they can be read when C_ENABLE_VIDPRMTR_READS is 1. </p>
</div></td></tr>
<tr class="memitem:ga4feada9ad41cf079a8c9b7c6aebfecff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga4feada9ad41cf079a8c9b7c6aebfecff">XAXIVDMA_VSIZE_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:ga4feada9ad41cf079a8c9b7c6aebfecff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vertical size.  <a href="group__axivdma__v6__0.html#ga4feada9ad41cf079a8c9b7c6aebfecff">More...</a><br /></td></tr>
<tr class="separator:ga4feada9ad41cf079a8c9b7c6aebfecff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa1752ade8b38bc29a8528859e634a38d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaa1752ade8b38bc29a8528859e634a38d">XAXIVDMA_HSIZE_OFFSET</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaa1752ade8b38bc29a8528859e634a38d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Horizontal size.  <a href="group__axivdma__v6__0.html#gaa1752ade8b38bc29a8528859e634a38d">More...</a><br /></td></tr>
<tr class="separator:gaa1752ade8b38bc29a8528859e634a38d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e165469c0c5618932b44f17dcfa566b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga5e165469c0c5618932b44f17dcfa566b">XAXIVDMA_STRD_FRMDLY_OFFSET</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga5e165469c0c5618932b44f17dcfa566b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Horizontal size.  <a href="group__axivdma__v6__0.html#ga5e165469c0c5618932b44f17dcfa566b">More...</a><br /></td></tr>
<tr class="separator:ga5e165469c0c5618932b44f17dcfa566b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga73ce4a1f2caf365b8c54cd77827a29cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga73ce4a1f2caf365b8c54cd77827a29cc">XAXIVDMA_START_ADDR_OFFSET</a>&#160;&#160;&#160;0x0000000C</td></tr>
<tr class="memdesc:ga73ce4a1f2caf365b8c54cd77827a29cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start of address.  <a href="group__axivdma__v6__0.html#ga73ce4a1f2caf365b8c54cd77827a29cc">More...</a><br /></td></tr>
<tr class="separator:ga73ce4a1f2caf365b8c54cd77827a29cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba552b4bc0c96fb9d76ef37e9fc34da7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaba552b4bc0c96fb9d76ef37e9fc34da7">XAXIVDMA_START_ADDR_LEN</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaba552b4bc0c96fb9d76ef37e9fc34da7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Each entry is 4 bytes.  <a href="group__axivdma__v6__0.html#gaba552b4bc0c96fb9d76ef37e9fc34da7">More...</a><br /></td></tr>
<tr class="separator:gaba552b4bc0c96fb9d76ef37e9fc34da7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga83c97295f4a50d39cacbb32fa928ea95"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga83c97295f4a50d39cacbb32fa928ea95">XAXIVDMA_START_ADDR_MSB_OFFSET</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga83c97295f4a50d39cacbb32fa928ea95"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start of address.  <a href="group__axivdma__v6__0.html#ga83c97295f4a50d39cacbb32fa928ea95">More...</a><br /></td></tr>
<tr class="separator:ga83c97295f4a50d39cacbb32fa928ea95"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks of the XAXIVDMA_CR_OFFSET register</div></td></tr>
<tr class="memitem:gaf6165b2a5668ffbfe3320c83f1a3ffaa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaf6165b2a5668ffbfe3320c83f1a3ffaa">XAXIVDMA_CR_RUNSTOP_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaf6165b2a5668ffbfe3320c83f1a3ffaa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start/stop DMA channel.  <a href="group__axivdma__v6__0.html#gaf6165b2a5668ffbfe3320c83f1a3ffaa">More...</a><br /></td></tr>
<tr class="separator:gaf6165b2a5668ffbfe3320c83f1a3ffaa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6bda812084d25429b793e441c698298d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga6bda812084d25429b793e441c698298d">XAXIVDMA_CR_TAIL_EN_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga6bda812084d25429b793e441c698298d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tail ptr enable or Park.  <a href="group__axivdma__v6__0.html#ga6bda812084d25429b793e441c698298d">More...</a><br /></td></tr>
<tr class="separator:ga6bda812084d25429b793e441c698298d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaacbafb1fba1bc73bd5ed95b06a5cb4f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaacbafb1fba1bc73bd5ed95b06a5cb4f5">XAXIVDMA_CR_RESET_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaacbafb1fba1bc73bd5ed95b06a5cb4f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset channel.  <a href="group__axivdma__v6__0.html#gaacbafb1fba1bc73bd5ed95b06a5cb4f5">More...</a><br /></td></tr>
<tr class="separator:gaacbafb1fba1bc73bd5ed95b06a5cb4f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac70dd163b5142c5211e349e16f980e11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gac70dd163b5142c5211e349e16f980e11">XAXIVDMA_CR_SYNC_EN_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gac70dd163b5142c5211e349e16f980e11"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gen-lock enable.  <a href="group__axivdma__v6__0.html#gac70dd163b5142c5211e349e16f980e11">More...</a><br /></td></tr>
<tr class="separator:gac70dd163b5142c5211e349e16f980e11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabfed305b44e791eaae8142ab94bd0ba9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gabfed305b44e791eaae8142ab94bd0ba9">XAXIVDMA_CR_FRMCNT_EN_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gabfed305b44e791eaae8142ab94bd0ba9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frame count enable.  <a href="group__axivdma__v6__0.html#gabfed305b44e791eaae8142ab94bd0ba9">More...</a><br /></td></tr>
<tr class="separator:gabfed305b44e791eaae8142ab94bd0ba9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7af6342cb5f43fa2036b3fbc8be1a082"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga7af6342cb5f43fa2036b3fbc8be1a082">XAXIVDMA_CR_FSYNC_SRC_MASK</a>&#160;&#160;&#160;0x00000060</td></tr>
<tr class="memdesc:ga7af6342cb5f43fa2036b3fbc8be1a082"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fsync Source Select.  <a href="group__axivdma__v6__0.html#ga7af6342cb5f43fa2036b3fbc8be1a082">More...</a><br /></td></tr>
<tr class="separator:ga7af6342cb5f43fa2036b3fbc8be1a082"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac2bf28150cc3fc0d8cd0fceeedf60554"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gac2bf28150cc3fc0d8cd0fceeedf60554">XAXIVDMA_CR_GENLCK_SRC_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gac2bf28150cc3fc0d8cd0fceeedf60554"><td class="mdescLeft">&#160;</td><td class="mdescRight">Genlock Source Select.  <a href="group__axivdma__v6__0.html#gac2bf28150cc3fc0d8cd0fceeedf60554">More...</a><br /></td></tr>
<tr class="separator:gac2bf28150cc3fc0d8cd0fceeedf60554"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa5247e7518945ca4123cff1a2f2d8476"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaa5247e7518945ca4123cff1a2f2d8476">XAXIVDMA_CR_RD_PTR_MASK</a>&#160;&#160;&#160;0x00000F00</td></tr>
<tr class="memdesc:gaa5247e7518945ca4123cff1a2f2d8476"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read pointer number.  <a href="group__axivdma__v6__0.html#gaa5247e7518945ca4123cff1a2f2d8476">More...</a><br /></td></tr>
<tr class="separator:gaa5247e7518945ca4123cff1a2f2d8476"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga627a79cc1c66dfbd98783d7f053fdd36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga627a79cc1c66dfbd98783d7f053fdd36">XAXIVDMA_CR_GENLCK_RPT_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:ga627a79cc1c66dfbd98783d7f053fdd36"><td class="mdescLeft">&#160;</td><td class="mdescRight">GenLock Repeat.  <a href="group__axivdma__v6__0.html#ga627a79cc1c66dfbd98783d7f053fdd36">More...</a><br /></td></tr>
<tr class="separator:ga627a79cc1c66dfbd98783d7f053fdd36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe377bb760c2aa781930960549690b87"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gafe377bb760c2aa781930960549690b87">XAXIVDMA_CR_RD_PTR_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gafe377bb760c2aa781930960549690b87"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for read pointer number.  <a href="group__axivdma__v6__0.html#gafe377bb760c2aa781930960549690b87">More...</a><br /></td></tr>
<tr class="separator:gafe377bb760c2aa781930960549690b87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks of the XAXIVDMA_SR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register reports status of a DMA channel, including run/stop/idle state, errors, and interrupts </p>
</div></td></tr>
<tr class="memitem:ga950f0fc166fb91f145538984a3b3f29f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga950f0fc166fb91f145538984a3b3f29f">XAXIVDMA_SR_HALTED_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga950f0fc166fb91f145538984a3b3f29f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA channel halted.  <a href="group__axivdma__v6__0.html#ga950f0fc166fb91f145538984a3b3f29f">More...</a><br /></td></tr>
<tr class="separator:ga950f0fc166fb91f145538984a3b3f29f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3ebc688ce8c9515277296cd7c9d9d68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gad3ebc688ce8c9515277296cd7c9d9d68">XAXIVDMA_SR_IDLE_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gad3ebc688ce8c9515277296cd7c9d9d68"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA channel idle.  <a href="group__axivdma__v6__0.html#gad3ebc688ce8c9515277296cd7c9d9d68">More...</a><br /></td></tr>
<tr class="separator:gad3ebc688ce8c9515277296cd7c9d9d68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga73f14cc8e7e2905ed537d3848b31c23b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga73f14cc8e7e2905ed537d3848b31c23b">XAXIVDMA_SR_ERR_INTERNAL_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga73f14cc8e7e2905ed537d3848b31c23b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Datamover internal err.  <a href="group__axivdma__v6__0.html#ga73f14cc8e7e2905ed537d3848b31c23b">More...</a><br /></td></tr>
<tr class="separator:ga73f14cc8e7e2905ed537d3848b31c23b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga08d366ceff80640f727d34668680f7a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga08d366ceff80640f727d34668680f7a0">XAXIVDMA_SR_ERR_SLAVE_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga08d366ceff80640f727d34668680f7a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Datamover slave err.  <a href="group__axivdma__v6__0.html#ga08d366ceff80640f727d34668680f7a0">More...</a><br /></td></tr>
<tr class="separator:ga08d366ceff80640f727d34668680f7a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaafc34ba20bfb44a6132fb677b4a28d9d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaafc34ba20bfb44a6132fb677b4a28d9d">XAXIVDMA_SR_ERR_DECODE_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gaafc34ba20bfb44a6132fb677b4a28d9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Datamover decode err.  <a href="group__axivdma__v6__0.html#gaafc34ba20bfb44a6132fb677b4a28d9d">More...</a><br /></td></tr>
<tr class="separator:gaafc34ba20bfb44a6132fb677b4a28d9d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e70b134baebf4f1a124700d8601325b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga5e70b134baebf4f1a124700d8601325b">XAXIVDMA_SR_ERR_FSZ_LESS_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga5e70b134baebf4f1a124700d8601325b"><td class="mdescLeft">&#160;</td><td class="mdescRight">FSize Less Mismatch err.  <a href="group__axivdma__v6__0.html#ga5e70b134baebf4f1a124700d8601325b">More...</a><br /></td></tr>
<tr class="separator:ga5e70b134baebf4f1a124700d8601325b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b94d44f1347a7c92370f63855015ba4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga8b94d44f1347a7c92370f63855015ba4">XAXIVDMA_SR_ERR_LSZ_LESS_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga8b94d44f1347a7c92370f63855015ba4"><td class="mdescLeft">&#160;</td><td class="mdescRight">LSize Less Mismatch err.  <a href="group__axivdma__v6__0.html#ga8b94d44f1347a7c92370f63855015ba4">More...</a><br /></td></tr>
<tr class="separator:ga8b94d44f1347a7c92370f63855015ba4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga30c9fca88a18c4bcde79ddf03cd6d240"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga30c9fca88a18c4bcde79ddf03cd6d240">XAXIVDMA_SR_ERR_SG_SLV_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga30c9fca88a18c4bcde79ddf03cd6d240"><td class="mdescLeft">&#160;</td><td class="mdescRight">SG slave err.  <a href="group__axivdma__v6__0.html#ga30c9fca88a18c4bcde79ddf03cd6d240">More...</a><br /></td></tr>
<tr class="separator:ga30c9fca88a18c4bcde79ddf03cd6d240"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga228552801c02459e8941f66b55aee2fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga228552801c02459e8941f66b55aee2fe">XAXIVDMA_SR_ERR_SG_DEC_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:ga228552801c02459e8941f66b55aee2fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">SG decode err.  <a href="group__axivdma__v6__0.html#ga228552801c02459e8941f66b55aee2fe">More...</a><br /></td></tr>
<tr class="separator:ga228552801c02459e8941f66b55aee2fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga27f1501ec6a048b6afa3e66720d971e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga27f1501ec6a048b6afa3e66720d971e3">XAXIVDMA_SR_ERR_FSZ_MORE_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:ga27f1501ec6a048b6afa3e66720d971e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">FSize More Mismatch err.  <a href="group__axivdma__v6__0.html#ga27f1501ec6a048b6afa3e66720d971e3">More...</a><br /></td></tr>
<tr class="separator:ga27f1501ec6a048b6afa3e66720d971e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9fe7dc9348c9a4aed7eb2f671e62dda7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga9fe7dc9348c9a4aed7eb2f671e62dda7">XAXIVDMA_SR_ERR_ALL_MASK</a>&#160;&#160;&#160;0x00000FF0</td></tr>
<tr class="memdesc:ga9fe7dc9348c9a4aed7eb2f671e62dda7"><td class="mdescLeft">&#160;</td><td class="mdescRight">All errors.  <a href="group__axivdma__v6__0.html#ga9fe7dc9348c9a4aed7eb2f671e62dda7">More...</a><br /></td></tr>
<tr class="separator:ga9fe7dc9348c9a4aed7eb2f671e62dda7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for interrupts</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These masks are shared by the XAXIVDMA_CR_OFFSET register and the XAXIVDMA_SR_OFFSET register </p>
</div></td></tr>
<tr class="memitem:ga2f25fa1f54f8b95752ba1d303fc4a6b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga2f25fa1f54f8b95752ba1d303fc4a6b6">XAXIVDMA_IXR_FRMCNT_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:ga2f25fa1f54f8b95752ba1d303fc4a6b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frame count intr.  <a href="group__axivdma__v6__0.html#ga2f25fa1f54f8b95752ba1d303fc4a6b6">More...</a><br /></td></tr>
<tr class="separator:ga2f25fa1f54f8b95752ba1d303fc4a6b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad12fc5d30ab28f345d19e4034aea746e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gad12fc5d30ab28f345d19e4034aea746e">XAXIVDMA_IXR_DELAYCNT_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:gad12fc5d30ab28f345d19e4034aea746e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay interrupt.  <a href="group__axivdma__v6__0.html#gad12fc5d30ab28f345d19e4034aea746e">More...</a><br /></td></tr>
<tr class="separator:gad12fc5d30ab28f345d19e4034aea746e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga88ccc9e37f16a1b4ecffd5e09a4c8cfb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga88ccc9e37f16a1b4ecffd5e09a4c8cfb">XAXIVDMA_IXR_ERROR_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:ga88ccc9e37f16a1b4ecffd5e09a4c8cfb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error interrupt.  <a href="group__axivdma__v6__0.html#ga88ccc9e37f16a1b4ecffd5e09a4c8cfb">More...</a><br /></td></tr>
<tr class="separator:ga88ccc9e37f16a1b4ecffd5e09a4c8cfb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed70612ee26f1faf7699e301afda8048"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaed70612ee26f1faf7699e301afda8048">XAXIVDMA_IXR_COMPLETION_MASK</a>&#160;&#160;&#160;0x00003000</td></tr>
<tr class="memdesc:gaed70612ee26f1faf7699e301afda8048"><td class="mdescLeft">&#160;</td><td class="mdescRight">Completion interrupts.  <a href="group__axivdma__v6__0.html#gaed70612ee26f1faf7699e301afda8048">More...</a><br /></td></tr>
<tr class="separator:gaed70612ee26f1faf7699e301afda8048"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e80967b83e9f0f65dfde6c92008f0d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga6e80967b83e9f0f65dfde6c92008f0d2">XAXIVDMA_IXR_ALL_MASK</a>&#160;&#160;&#160;0x00007000</td></tr>
<tr class="memdesc:ga6e80967b83e9f0f65dfde6c92008f0d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">All interrupts.  <a href="group__axivdma__v6__0.html#ga6e80967b83e9f0f65dfde6c92008f0d2">More...</a><br /></td></tr>
<tr class="separator:ga6e80967b83e9f0f65dfde6c92008f0d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and shift for delay and coalesce</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These masks are shared by the XAXIVDMA_CR_OFFSET register and the XAXIVDMA_SR_OFFSET register </p>
</div></td></tr>
<tr class="memitem:gac556991d9307f211f770d15a117ee937"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gac556991d9307f211f770d15a117ee937">XAXIVDMA_DELAY_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:gac556991d9307f211f770d15a117ee937"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay timeout counter.  <a href="group__axivdma__v6__0.html#gac556991d9307f211f770d15a117ee937">More...</a><br /></td></tr>
<tr class="separator:gac556991d9307f211f770d15a117ee937"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf4ab4ba9a0c2984efad7fefe195fe0ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaf4ab4ba9a0c2984efad7fefe195fe0ed">XAXIVDMA_FRMCNT_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:gaf4ab4ba9a0c2984efad7fefe195fe0ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frame counter.  <a href="group__axivdma__v6__0.html#gaf4ab4ba9a0c2984efad7fefe195fe0ed">More...</a><br /></td></tr>
<tr class="separator:gaf4ab4ba9a0c2984efad7fefe195fe0ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad0d12f32fff3037d4b1316350e02fef6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gad0d12f32fff3037d4b1316350e02fef6">XAXIVDMA_REGINDEX_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gad0d12f32fff3037d4b1316350e02fef6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register Index.  <a href="group__axivdma__v6__0.html#gad0d12f32fff3037d4b1316350e02fef6">More...</a><br /></td></tr>
<tr class="separator:gad0d12f32fff3037d4b1316350e02fef6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadbbf73e481e88de57b05b66a7b2953be"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_DELAY_SHIFT</b>&#160;&#160;&#160;24</td></tr>
<tr class="separator:gadbbf73e481e88de57b05b66a7b2953be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa1327862b7b357444edd2fb689247f06"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_FRMCNT_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:gaa1327862b7b357444edd2fb689247f06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for the XAXIVDMA_CDESC_OFFSET register</div></td></tr>
<tr class="memitem:gac6d688599e8a9ffdf9c45bd7789f58cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gac6d688599e8a9ffdf9c45bd7789f58cc">XAXIVDMA_CDESC_CURBD_MASK</a>&#160;&#160;&#160;0xFFFFFFE0</td></tr>
<tr class="memdesc:gac6d688599e8a9ffdf9c45bd7789f58cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">BD now working on.  <a href="group__axivdma__v6__0.html#gac6d688599e8a9ffdf9c45bd7789f58cc">More...</a><br /></td></tr>
<tr class="separator:gac6d688599e8a9ffdf9c45bd7789f58cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for XAXIVDMA_TDESC_OFFSET register</div></td></tr>
<tr class="memitem:gaa47b0fa02c5e8f984bc17bf18cd379ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaa47b0fa02c5e8f984bc17bf18cd379ce">XAXIVDMA_TDESC_CURBD_MASK</a>&#160;&#160;&#160;0xFFFFFFE0</td></tr>
<tr class="memdesc:gaa47b0fa02c5e8f984bc17bf18cd379ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">BD to stop on.  <a href="group__axivdma__v6__0.html#gaa47b0fa02c5e8f984bc17bf18cd379ce">More...</a><br /></td></tr>
<tr class="separator:gaa47b0fa02c5e8f984bc17bf18cd379ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for XAXIVDMA_FRMSTORE_OFFSET register</div></td></tr>
<tr class="memitem:ga8391dd8e6cc064bdc591d311b25b0c3c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_FRMSTORE_MASK</b>&#160;&#160;&#160;0x0000003F</td></tr>
<tr class="separator:ga8391dd8e6cc064bdc591d311b25b0c3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for XAXIVDMA_PARKPTR_OFFSET register</div></td></tr>
<tr class="memitem:ga39001a9b8ae972fc53463961ca423ac1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga39001a9b8ae972fc53463961ca423ac1">XAXIVDMA_PARKPTR_READREF_MASK</a>&#160;&#160;&#160;0x0000001F</td></tr>
<tr class="memdesc:ga39001a9b8ae972fc53463961ca423ac1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read frame to park on.  <a href="group__axivdma__v6__0.html#ga39001a9b8ae972fc53463961ca423ac1">More...</a><br /></td></tr>
<tr class="separator:ga39001a9b8ae972fc53463961ca423ac1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9656852c690e3a7e5253fe67b87f10cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga9656852c690e3a7e5253fe67b87f10cf">XAXIVDMA_PARKPTR_WRTREF_MASK</a>&#160;&#160;&#160;0x00001F00</td></tr>
<tr class="memdesc:ga9656852c690e3a7e5253fe67b87f10cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write frame to park on.  <a href="group__axivdma__v6__0.html#ga9656852c690e3a7e5253fe67b87f10cf">More...</a><br /></td></tr>
<tr class="separator:ga9656852c690e3a7e5253fe67b87f10cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3326b79c706c90993eea1033edc5f304"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga3326b79c706c90993eea1033edc5f304">XAXIVDMA_PARKPTR_READSTR_MASK</a>&#160;&#160;&#160;0x001F0000</td></tr>
<tr class="memdesc:ga3326b79c706c90993eea1033edc5f304"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current read frame.  <a href="group__axivdma__v6__0.html#ga3326b79c706c90993eea1033edc5f304">More...</a><br /></td></tr>
<tr class="separator:ga3326b79c706c90993eea1033edc5f304"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafdf5ab4a765d1ed93a697b276d832b7d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gafdf5ab4a765d1ed93a697b276d832b7d">XAXIVDMA_PARKPTR_WRTSTR_MASK</a>&#160;&#160;&#160;0x1F000000</td></tr>
<tr class="memdesc:gafdf5ab4a765d1ed93a697b276d832b7d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current write frame.  <a href="group__axivdma__v6__0.html#gafdf5ab4a765d1ed93a697b276d832b7d">More...</a><br /></td></tr>
<tr class="separator:gafdf5ab4a765d1ed93a697b276d832b7d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0e834922f62a7d5d10e10936acf42b7c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_READREF_SHIFT</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:ga0e834922f62a7d5d10e10936acf42b7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8a3db8b7c54d3a33cf2856d04e8d3bd"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_WRTREF_SHIFT</b>&#160;&#160;&#160;8</td></tr>
<tr class="separator:gaf8a3db8b7c54d3a33cf2856d04e8d3bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5bcf9c65743d7dddf7025d7f2eeb2d70"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_READSTR_SHIFT</b>&#160;&#160;&#160;16</td></tr>
<tr class="separator:ga5bcf9c65743d7dddf7025d7f2eeb2d70"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga76a20e94c018639a564b71ec3c34dbe7"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_WRTSTR_SHIFT</b>&#160;&#160;&#160;24</td></tr>
<tr class="separator:ga76a20e94c018639a564b71ec3c34dbe7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e274c9f02af4538043f757c3e224a91"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga7e274c9f02af4538043f757c3e224a91">XAXIVDMA_FRM_MAX</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:ga7e274c9f02af4538043f757c3e224a91"><td class="mdescLeft">&#160;</td><td class="mdescRight">At most 16 frames.  <a href="group__axivdma__v6__0.html#ga7e274c9f02af4538043f757c3e224a91">More...</a><br /></td></tr>
<tr class="separator:ga7e274c9f02af4538043f757c3e224a91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for XAXIVDMA_VERSION_OFFSET register</div></td></tr>
<tr class="memitem:ga778f82c0f80720c8114b09dd840dd625"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga778f82c0f80720c8114b09dd840dd625">XAXIVDMA_VERSION_MAJOR_MASK</a>&#160;&#160;&#160;0xF0000000</td></tr>
<tr class="memdesc:ga778f82c0f80720c8114b09dd840dd625"><td class="mdescLeft">&#160;</td><td class="mdescRight">Major version.  <a href="group__axivdma__v6__0.html#ga778f82c0f80720c8114b09dd840dd625">More...</a><br /></td></tr>
<tr class="separator:ga778f82c0f80720c8114b09dd840dd625"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d2a6902e976af18d7486fe12d45ba9b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga5d2a6902e976af18d7486fe12d45ba9b">XAXIVDMA_VERSION_MINOR_MASK</a>&#160;&#160;&#160;0x0FF00000</td></tr>
<tr class="memdesc:ga5d2a6902e976af18d7486fe12d45ba9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Minor version.  <a href="group__axivdma__v6__0.html#ga5d2a6902e976af18d7486fe12d45ba9b">More...</a><br /></td></tr>
<tr class="separator:ga5d2a6902e976af18d7486fe12d45ba9b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae651c29e871bbdd802cecc9fb45948b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gae651c29e871bbdd802cecc9fb45948b3">XAXIVDMA_VERSION_REV_MASK</a>&#160;&#160;&#160;0x000F0000</td></tr>
<tr class="memdesc:gae651c29e871bbdd802cecc9fb45948b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Revision letter.  <a href="group__axivdma__v6__0.html#gae651c29e871bbdd802cecc9fb45948b3">More...</a><br /></td></tr>
<tr class="separator:gae651c29e871bbdd802cecc9fb45948b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7394eb6e7fe9e801acb30d4d776e7062"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_VERSION_MAJOR_SHIFT</b>&#160;&#160;&#160;28</td></tr>
<tr class="separator:ga7394eb6e7fe9e801acb30d4d776e7062"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7250fc83efc10927472e1dadf80295ea"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XAXIVDMA_VERSION_MINOR_SHIFT</b>&#160;&#160;&#160;20</td></tr>
<tr class="separator:ga7250fc83efc10927472e1dadf80295ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for XAXIVDMA_S2MM_IRQ_MASK_OFFSET register</div></td></tr>
<tr class="memitem:ga35e5cf93415d4b0f1973af8fca40bec6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga35e5cf93415d4b0f1973af8fca40bec6">XAXIVDMA_S2MM_IRQ_FSZLESS_SOF_ERLY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga35e5cf93415d4b0f1973af8fca40bec6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Masks S2MM IRQ FSize Less/SOF Early Error.  <a href="group__axivdma__v6__0.html#ga35e5cf93415d4b0f1973af8fca40bec6">More...</a><br /></td></tr>
<tr class="separator:ga35e5cf93415d4b0f1973af8fca40bec6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60eb583a54045686ff42ea1e93fd67dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga60eb583a54045686ff42ea1e93fd67dd">XAXIVDMA_S2MM_IRQ_LSZLESS_EOL_ERLY_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga60eb583a54045686ff42ea1e93fd67dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Masks S2MM IRQ LSize Less/EOL Early Error.  <a href="group__axivdma__v6__0.html#ga60eb583a54045686ff42ea1e93fd67dd">More...</a><br /></td></tr>
<tr class="separator:ga60eb583a54045686ff42ea1e93fd67dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga19f83bb8bcb2f6535463bcd03f39552e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga19f83bb8bcb2f6535463bcd03f39552e">XAXIVDMA_S2MM_IRQ_FSZMORE_SOF_LATE_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga19f83bb8bcb2f6535463bcd03f39552e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Masks S2MM IRQ FSize More/SOF Late Error.  <a href="group__axivdma__v6__0.html#ga19f83bb8bcb2f6535463bcd03f39552e">More...</a><br /></td></tr>
<tr class="separator:ga19f83bb8bcb2f6535463bcd03f39552e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0deb90d1e246708ed32ed905d56894e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga0deb90d1e246708ed32ed905d56894e9">XAXIVDMA_S2MM_IRQ_LSZMORE_EOL_LATE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga0deb90d1e246708ed32ed905d56894e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Masks S2MM IRQ LSize More/EOL Late Error.  <a href="group__axivdma__v6__0.html#ga0deb90d1e246708ed32ed905d56894e9">More...</a><br /></td></tr>
<tr class="separator:ga0deb90d1e246708ed32ed905d56894e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ba0af99c40314b1288a6a95ba2ee688"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga0ba0af99c40314b1288a6a95ba2ee688">XAXIVDMA_S2MM_IRQ_ERR_ALL_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:ga0ba0af99c40314b1288a6a95ba2ee688"><td class="mdescLeft">&#160;</td><td class="mdescRight">Masks all S2MM IRQ Errors.  <a href="group__axivdma__v6__0.html#ga0ba0af99c40314b1288a6a95ba2ee688">More...</a><br /></td></tr>
<tr class="separator:ga0ba0af99c40314b1288a6a95ba2ee688"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Frame Delay shared by start address registers and BDs</div></td></tr>
<tr class="memitem:ga8394a54d3cfaf11b3b824059d760d5d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga8394a54d3cfaf11b3b824059d760d5d8">XAXIVDMA_VSIZE_MASK</a>&#160;&#160;&#160;0x00001FFF</td></tr>
<tr class="memdesc:ga8394a54d3cfaf11b3b824059d760d5d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vertical size.  <a href="group__axivdma__v6__0.html#ga8394a54d3cfaf11b3b824059d760d5d8">More...</a><br /></td></tr>
<tr class="separator:ga8394a54d3cfaf11b3b824059d760d5d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3fbf84b20d6e4639e658a99c03a300b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga3fbf84b20d6e4639e658a99c03a300b6">XAXIVDMA_HSIZE_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga3fbf84b20d6e4639e658a99c03a300b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Horizontal size.  <a href="group__axivdma__v6__0.html#ga3fbf84b20d6e4639e658a99c03a300b6">More...</a><br /></td></tr>
<tr class="separator:ga3fbf84b20d6e4639e658a99c03a300b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac73189f5e640fc37597a0559e67e7dce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gac73189f5e640fc37597a0559e67e7dce">XAXIVDMA_STRIDE_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:gac73189f5e640fc37597a0559e67e7dce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stride size.  <a href="group__axivdma__v6__0.html#gac73189f5e640fc37597a0559e67e7dce">More...</a><br /></td></tr>
<tr class="separator:gac73189f5e640fc37597a0559e67e7dce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga76abb6dc712998f6165b074dccc4670e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga76abb6dc712998f6165b074dccc4670e">XAXIVDMA_FRMDLY_MASK</a>&#160;&#160;&#160;0x0F000000</td></tr>
<tr class="memdesc:ga76abb6dc712998f6165b074dccc4670e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frame delay.  <a href="group__axivdma__v6__0.html#ga76abb6dc712998f6165b074dccc4670e">More...</a><br /></td></tr>
<tr class="separator:ga76abb6dc712998f6165b074dccc4670e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga266367de39275d3e11a96966a4039130"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga266367de39275d3e11a96966a4039130">XAXIVDMA_FRMDLY_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:ga266367de39275d3e11a96966a4039130"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for frame delay.  <a href="group__axivdma__v6__0.html#ga266367de39275d3e11a96966a4039130">More...</a><br /></td></tr>
<tr class="separator:ga266367de39275d3e11a96966a4039130"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Buffer Descriptor offsets</div></td></tr>
<tr class="memitem:gaf78dbbcc98154cea4b2447f6c84bc3f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaf78dbbcc98154cea4b2447f6c84bc3f4">XAXIVDMA_BD_NDESC_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:gaf78dbbcc98154cea4b2447f6c84bc3f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Next descriptor pointer.  <a href="group__axivdma__v6__0.html#gaf78dbbcc98154cea4b2447f6c84bc3f4">More...</a><br /></td></tr>
<tr class="separator:gaf78dbbcc98154cea4b2447f6c84bc3f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga304b699c1cacbc7fe6f13b3c8f1e2b2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga304b699c1cacbc7fe6f13b3c8f1e2b2f">XAXIVDMA_BD_START_ADDR_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:ga304b699c1cacbc7fe6f13b3c8f1e2b2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start address.  <a href="group__axivdma__v6__0.html#ga304b699c1cacbc7fe6f13b3c8f1e2b2f">More...</a><br /></td></tr>
<tr class="separator:ga304b699c1cacbc7fe6f13b3c8f1e2b2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf5da523f9ccd58f988968f7cc10b23e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaf5da523f9ccd58f988968f7cc10b23e1">XAXIVDMA_BD_VSIZE_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:gaf5da523f9ccd58f988968f7cc10b23e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vertical size.  <a href="group__axivdma__v6__0.html#gaf5da523f9ccd58f988968f7cc10b23e1">More...</a><br /></td></tr>
<tr class="separator:gaf5da523f9ccd58f988968f7cc10b23e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae76e8ca3b5117820ba1a23dab5e7a8e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gae76e8ca3b5117820ba1a23dab5e7a8e4">XAXIVDMA_BD_HSIZE_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:gae76e8ca3b5117820ba1a23dab5e7a8e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Horizontal size.  <a href="group__axivdma__v6__0.html#gae76e8ca3b5117820ba1a23dab5e7a8e4">More...</a><br /></td></tr>
<tr class="separator:gae76e8ca3b5117820ba1a23dab5e7a8e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga260f7451d08e9e3afa7108a5af67e838"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga260f7451d08e9e3afa7108a5af67e838">XAXIVDMA_BD_STRIDE_OFFSET</a>&#160;&#160;&#160;0x18</td></tr>
<tr class="memdesc:ga260f7451d08e9e3afa7108a5af67e838"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stride size.  <a href="group__axivdma__v6__0.html#ga260f7451d08e9e3afa7108a5af67e838">More...</a><br /></td></tr>
<tr class="separator:ga260f7451d08e9e3afa7108a5af67e838"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1af4c3afa712d97d3f1af8153c9fb48"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaf1af4c3afa712d97d3f1af8153c9fb48">XAXIVDMA_BD_NUM_WORDS</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:gaf1af4c3afa712d97d3f1af8153c9fb48"><td class="mdescLeft">&#160;</td><td class="mdescRight">Total number of words for one BD.  <a href="group__axivdma__v6__0.html#gaf1af4c3afa712d97d3f1af8153c9fb48">More...</a><br /></td></tr>
<tr class="separator:gaf1af4c3afa712d97d3f1af8153c9fb48"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab253772ebf384b0e4962efafa11916fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gab253772ebf384b0e4962efafa11916fb">XAXIVDMA_BD_HW_NUM_BYTES</a>&#160;&#160;&#160;28</td></tr>
<tr class="memdesc:gab253772ebf384b0e4962efafa11916fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of bytes hw used.  <a href="group__axivdma__v6__0.html#gab253772ebf384b0e4962efafa11916fb">More...</a><br /></td></tr>
<tr class="separator:gab253772ebf384b0e4962efafa11916fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga80f15b7cc612ff34dfa70ef2a5283fbd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga80f15b7cc612ff34dfa70ef2a5283fbd">XAXIVDMA_BD_BYTES_TO_CLEAR</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:ga80f15b7cc612ff34dfa70ef2a5283fbd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Skip next ptr when clearing.  <a href="group__axivdma__v6__0.html#ga80f15b7cc612ff34dfa70ef2a5283fbd">More...</a><br /></td></tr>
<tr class="separator:ga80f15b7cc612ff34dfa70ef2a5283fbd"><td class="memSeparator" colspan="2">&#160;</td></tr>
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